Data converters are provided for receiving either an analog signal for conversion to a digital signal or a digital signal for conversion to analog signal. For conversion of analog signals to digital signals, an analog-to-digital converter is utilized. This is typically facilitated by sampling an analog voltage onto a capacitor array having a plurality of binary weighted capacitors. The capacitors then have the ability to have one plate thereof selectively switched between a reference voltage and ground to redistribute the charge among the capacitors, the switching done in a sequential manner in accordance with a successive approximation algorithm. By selectively switching the plates of the capacitors, and comparing the other plate of the capacitors, which is connected to a common input of a comparator, to a reference voltage, a digital value for the analog voltage sampled at the input can be determined.
A number of problems exist with the data conversion of an analog signal to a digital signal. Some of these problems reside in the various offsets of the inputs to the comparators, one of which is due to the fact that the actual chip ground may be different from the input ground at the PC board on which the actual chip is disposed. Additionally, the capacitors in the capacitor array are weighted and can have errors associated therewith. These errors can be accounted for by actually calibrating each of the capacitors with a sub-capacitor array. However, this calibration must be done at each power up of the A/D convertor. Additionally, these capacitor arrays can also have various parasitics associated therewith that effect the operation thereof and require the driving voltage to drive a higher capacitance value than that associated with the capacitance array.
When the capacitor arrays are operated in accordance with a data conversion algorithm such as a SAR algorithm, during the sampling period, the output node of the capacitor array is typically connected to an input of an amplifier and that input connected to a reference voltage. When operating in conjunction with a differential input amplifier, typically both input nodes thereof are switched to a common mode voltage during the sampling or tracking phase where the input voltage is impressed across the switched capacitors and then switched to the capacitor array thereafter. However, it is important when operating with a single array that noise introduction by the voltage source driving the common mode node or reference node for each of the inputs is cancelled. Unless these are balanced, there will be a noise contribution due to this reference voltage circuit.
In a switched capacitor array, the capacitors are binary-weighted with the array that is subjected to a charge-redistribution successive approximation algorithm. However, in order to maintain accuracy, the binary weighting must be accurate to within a certain tolerance. Any variation in these capacitor values will cause errors in the data conversion operation. To eliminate process related capacitor variations, trim capacitors have been utilized that are disposed in parallel with the capacitors in the switched capacitor array for varying value thereof. The capacitors could be “manually” trimmed such that the value thereof is varied at the time of test, or there could be a plurality of capacitors that are switched in parallel to each of the capacitors, such that each of the capacitors in the switched-capacitor array has a calibration array associated therewith. In order to determine the values of the trim capacitors in each of the calibration sub-arrays, at power-up, a calibration program is initiated and the value of the capacitors in the sub-arrays determined and then loaded into a calibration register. One technique for this is described in U.S. Pat. No. 4,709,225, issued Nov. 24, 1987. This system utilizes a plurality of sub-arrays that are disposed adjacent the primary capacitors in the switch type capacitor array. A comparator utilized in the successive approximation operation is utilized.